Semiconductor device and method for fabricating the same

ABSTRACT

A semiconductor device may include a substrate, a first nanowire, a gate electrode, a first gate spacer, a second gate spacer, a source/drain and a spacer connector. The first nanowire may be extended in a first direction and spaced apart from the substrate. The gate electrode may surround a periphery of the first nanowire, and extend in a second direction intersecting the first direction, and include first and second sidewalls opposite to each other. The first gate spacer may be formed on the first sidewall of the gate electrode. The first nanowire may pass through the first gate spacer. The second gate spacer may be formed on the second sidewall of the gate electrode. The first nanowire may pass through the second gate spacer. The source/drain may be disposed on at least one side of the gate electrode and connected with the first nanowire. The spacer connector may be disposed between the first nanowire and the substrate. The spacer connector may connect the first gate spacer and the second gate spacer to each other.

CROSS-REFERENCE TO RELATED APPLICATION

This U.S. non-provisional patent application claims priority under 35U.S.C. §119 to Korean Patent Application No. 10-2016-0025047, filed onMar. 2, 2016, the contents of which are hereby incorporated herein byreference in their entirety.

FIELD

The example embodiments of the inventive concepts generally relate to asemiconductor device and a method of fabricating the same.

BACKGROUND

Multi-gate transistors have been suggested to integrate more transistorswithout degrading performances thereof. Some multi-gate transistorsinclude three-dimensional channels. Current control capability ofmulti-gate transistors may be increased without increasing gate lengthsthereof. Further, short channel effect (SCE) may be suppressed.

SUMMARY

One embodiment of the inventive concept provides a semiconductor devicewith improved operating characteristics.

Another embodiment of the inventive concept provides a method offabricating a semiconductor device with improved operatingcharacteristics.

According to example embodiments of the inventive concept, asemiconductor device may include a substrate, a first nanowire, a gateelectrode, a first gate spacer, a second gate spacer, a source/drain anda spacer connector. The first nanowire may be extended in a firstdirection and spaced apart from the substrate. The gate electrode maysurround a periphery of the first nanowire, and may extend in a seconddirection intersecting the first direction, and may include first andsecond sidewalls opposite to each other. The first gate spacer may beformed on the first sidewall of the gate electrode. The first nanowiremay pass through the first gate spacer. The second gate spacer may beformed on the second sidewall of the gate electrode. The first nanowiremay pass through the second gate spacer. The source/drain may bedisposed on at least one side of the gate electrode and connected withthe first nanowire. The spacer connector may be disposed between thefirst nanowire and the substrate. The spacer connector may connect thefirst gate spacer and the second gate spacer to each other.

According to example embodiments of the inventive concept, asemiconductor device may include a substrate, a first nanowire, a gateelectrode, a gate spacer, a source/drain and an inner spacer. The firstnanowire may be extended in a first direction and spaced apart from thesubstrate. The gate electrode may surround a periphery of the firstnanowire, and may extend in a second direction intersecting the firstdirection. A gate spacer may be disposed on a sidewall of the gateelectrode. The gate spacer may include inner and outer sidewallsopposite to each other, and the inner sidewall of the gate spacer facesthe gate electrode. A source/drain may be disposed on at least one sideof the gate electrode and connected with the first nanowire. The firstnanowire may pass through the gate spacer to be connected to thesource/drain. An inner spacer may include a protruding portion disposedbetween the substrate and the first nanowire and contacting a lowersurface of the first nanowire, and a spaced portion connected to theprotruding portion and spaced apart from the lower surface of the firstnanowire.

According to example embodiments of the inventive concept, a method offabricating a semiconductor device may include forming a fin-typestructure extending in a first direction on a substrate and having afirst semiconductor pattern, a second semiconductor pattern and a thirdsemiconductor pattern, the second and third semiconductor patterns beingalternatively stacked on the first semiconductor pattern, forming adummy gate electrode on the fin-type structure, the dummy gate electrodeintersecting the fin-type structure and extending in a second directiondifferent from the first direction, forming a first spacer on thesidewall of the dummy gate electrode, removing a portion of the fin-typestructure which is not overlapped with the dummy gate electrode and thefirst spacer to form a recess within the fin-type structure, removing atleast a portion of the second semiconductor pattern which is exposed bythe recess and overlapped with the first spacer to form a dimple,completely removing the first semiconductor pattern exposed by therecess to form a through hole, forming an inner spacer layer filling thedimple and the through hole, removing a portion of the inner spacerlayer to form an upper inner spacer in the dimple and a lower innerspacer in the through hole, and forming a source/drain filling therecess.

According to example embodiments of the inventive concept, asemiconductor device, may include: a substrate; a first nanowireextended in a first direction and spaced apart from the substrate; agate electrode surrounding a periphery of the first nanowire andextending in a second direction intersecting the first direction; a gatespacer disposed on a sidewall of the gate electrode, wherein the gatespacer comprises inner and outer sidewalls opposite to each other, andthe inner sidewall of the gate spacer faces the gate electrode; asource/drain disposed on at least one side of the gate electrode andconnected with the first nanowire, wherein the first nanowire passesthrough the gate spacer to be connected to the source/drain; and aninner spacer disposed between the substrate and the first nanowire,wherein a material included in the gate spacer has a first dielectricconstant and a material included in the inner spacer has a seconddielectric constant different from the first dielectric constant.

BRIEF DESCRIPTION OF THE DRAWINGS

Some embodiments will be more clearly understood from the followingbrief description taken in conjunction with the accompanying drawings.The accompanying drawings represent non-limiting example embodiments asdescribed herein.

FIG. 1 is a perspective view illustrating a semiconductor deviceaccording to some example embodiments of the inventive concept.

FIG. 2 is a cross-sectional view taken along line A-A′ of FIG. 1.

FIG. 3 is a perspective view illustrating an inner spacer of FIG. 2 indetail.

FIG. 4 is a cross-sectional view taken along line B-B′ of FIG. 1.

FIG. 5 is a cross-sectional view taken along line C-C′ of FIG. 1.

FIG. 6 is a cross-sectional view illustrating an outer spacer and aninner spacer of FIG. 5 in detail.

FIG. 7 is a cross-sectional view illustrating a semiconductor deviceaccording to some example embodiments of the inventive concept.

FIG. 8 is a cross-sectional view illustrating the semiconductor deviceof FIG. 7.

FIG. 9 is a cross-sectional view illustrating an inner spacer and anouter spacer of FIG. 8 in detail.

FIG. 10 is a cross-sectional view illustrating a semiconductor deviceaccording to some example embodiments of the inventive concept.

FIG. 11 is a cross-sectional view illustrating the semiconductor deviceof FIG. 10.

FIG. 12 is a cross-sectional view illustrating the semiconductor deviceof FIG. 10.

FIG. 13 is a cross-sectional view illustrating a semiconductor deviceaccording to some example embodiments of the inventive concept.

FIG. 14 is a cross-sectional view illustrating the semiconductor deviceof FIG. 13.

FIG. 15 is a cross-sectional view illustrating the semiconductor deviceof FIG. 13.

FIG. 16 is a cross-sectional view illustrating a semiconductor deviceaccording to some example embodiments of the inventive concept.

FIG. 17 is a cross-sectional view illustrating the semiconductor deviceof FIG. 16.

FIG. 18 is a cross-sectional view illustrating the semiconductor deviceof FIG. 16.

FIGS. 19 to 36 are drawings illustrating a method for fabricating asemiconductor device according to example embodiments of the inventiveconcept.

FIG. 37 is a block diagram of an electronic system comprising asemiconductor device according to some example embodiments of theinventive concept.

FIGS. 38 and 39 illustrate exemplary semiconductor system including asemiconductor device according to an example embodiment.

It should be noted that these figures are intended to illustrate thegeneral characteristics of methods, structures and/or materials utilizedin certain some embodiments and to supplement the written descriptionprovided below. These drawings may not, however, be to scale and may notprecisely reflect the precise structural or performance characteristicsof any given embodiment, and should not be interpreted as limiting therange of values or properties encompassed by some embodiments. Forexample, the relative thicknesses and positioning of molecules, layers,regions and/or structural elements may be reduced or exaggerated forclarity. The use of similar or identical reference numbers in thevarious drawings is intended to indicate the presence of a similar oridentical element or feature.

DETAILED DESCRIPTION

The present disclosure now will be described more fully hereinafter withreference to the accompanying drawings, in which various embodiments areshown. The invention may, however, be embodied in many different formsand should not be construed as limited to the example embodiments setforth herein. These example embodiments are just that—examples—and manyimplementations and variations are possible that do not require thedetails provided herein. It should also be emphasized that thedisclosure provides details of alternative examples, but such listing ofalternatives is not exhaustive. Furthermore, any consistency of detailbetween various examples should not be interpreted as requiring suchdetail—it is impracticable to list every possible variation for everyfeature described herein. The language of the claims should bereferenced in determining the requirements of the invention.

Though the different figures show variations of exemplary embodiments,these figures are not necessarily intended to be mutually exclusive fromeach other. Rather, as will be seen from the context of the detaileddescription below, certain features depicted and described in differentfigures can be combined with other features from other figures to resultin various embodiments, when taking the figures and their description asa whole into consideration.

It will be understood that when an element is referred to as being“connected” or “coupled” to another element, it can be directlyconnected or coupled to the other element or intervening elements may bepresent. In contrast, when an element is referred to as being “directlyconnected” or “directly coupled” to another element, there are nointervening elements present. Other words used to describe therelationship between elements or layers should be interpreted in a likefashion (e.g., “between” versus “directly between,” “adjacent” versus“directly adjacent,” “on” versus “directly on”). The term “contact” or“in contact with” as used herein refers to a direct connection (e.g.,touching).

It will be understood that, although the terms “first”, “second”, etc,may be used herein to describe various elements, components, regions,layers and/or sections, these elements, components, regions, layersand/or sections should not be limited by these terms. These terms areonly used to distinguish one element, component, region, layer orsection from another element, component, region, layer or section. Thus,a first element, component, region, layer or section discussed belowcould be termed a second element, component, region, layer or sectionwithout departing from the teachings of some embodiments.

Spatially relative terms, such as “beneath,” “below,” “lower,” “above,”“upper” and the like, may be used herein for ease of description todescribe one element or feature's relationship to another element(s) orfeature(s) as illustrated in the figures. It will be understood that thespatially relative terms are intended to encompass differentorientations of the device in use or operation in addition to theorientation depicted in the figures. For example, if the device in thefigures is turned over, elements described as “below” or “beneath” otherelements or features would then be oriented “above” the other elementsor features. Thus, the exemplary term “below” can encompass both anorientation of above and below. The device may be otherwise oriented(rotated 90 degrees or at other orientations) and the spatially relativedescriptors used herein interpreted accordingly.

Terms such as “same,” “equal,” “planar,” or “coplanar,” as used hereinwhen referring to orientation, layout, location, shapes, sizes, amounts,or other measures do not necessarily mean an exactly identicalorientation, layout, location, shape, size, amount, or other measure,but are intended to encompass nearly identical orientation, layout,location, shapes, sizes, amounts, or other measures within acceptablevariations that may occur, for example, due to manufacturing processes.The term “substantially” may be used herein to emphasize this meaning,unless the context or other statements indicate otherwise. For example,items described as “substantially the same,” “substantially equal,” or“substantially planar,” may be exactly the same, equal, or planar, ormay be the same, equal, or planar within acceptable variations that mayoccur, for example, due to manufacturing processes.

Some embodiments of the inventive concepts are described herein withreference to cross-sectional illustrations that are schematicillustrations of idealized embodiments (and intermediate structures) ofsome embodiments. As such, variations from the shapes of theillustrations as a result, for example, of manufacturing techniquesand/or tolerances, are to be expected. Thus, some embodiments of theinventive concepts should not be construed as limited to the particularshapes of regions illustrated herein but are to include deviations inshapes that result, for example, from manufacturing. For example, animplanted region illustrated as a rectangle may have rounded or curvedfeatures and/or a gradient of implant concentration at its edges ratherthan a binary change from implanted to non-implanted region. Likewise, aburied region formed by implantation may result in some implantation inthe region between the buried region and the surface through which theimplantation takes place. Thus, the regions illustrated in the figuresare schematic in nature and their shapes are not intended to limit thescope of some embodiments.

Hereinafter, a semiconductor device according to some exampleembodiments of the inventive concept will be explained with reference toFIGS. 1 to 6.

FIG. 1 is a perspective view illustrating a semiconductor deviceaccording to some example embodiments of the inventive concept, and FIG.2 is a cross-sectional view taken along line A-A′ of FIG. 1. FIG. 3 is aperspective view illustrating an inner spacer of FIG. 2 in detail, andFIG. 4 is a cross-sectional view taken along line B-B′ of FIG. 1. FIG. 5is a cross-sectional view taken along line C-C′ of FIG. 1, and FIG. 6 isa cross-sectional view illustrating an outer spacer and an inner spacerof FIG. 5 in detail.

As used herein, a semiconductor device may refer to a device such as asemiconductor chip (e.g., memory chip and/or logic chip formed on adie), a stack of semiconductor chips, a semiconductor package includingone or more semiconductor chips stacked on a package substrate, or apackage-on-package device including a plurality of packages. Thesedevices may be formed using ball grid arrays, wire bonding, throughsubstrate vias, or other electrical connection elements, and may includememory devices such as volatile or non-volatile memory devices.

An electronic device, as used herein, may refer to these semiconductordevices, but may additionally include products that include thesedevices, such as a memory module, memory card, hard drive includingadditional components, or a mobile phone, laptop, tablet, desktop,camera, or other consumer electronic device, etc.

Referring to FIGS. 1 and 2, a semiconductor device may include afin-type pattern 110, a first nanowire 120, a gate electrode 130, a gatespacer 140 and a source/drain 150.

A substrate 100 may include, for example, bulk silicon orsilicon-on-insulator (SOI). Alternatively, the substrate 100 may be asilicon substrate, or may include other substances such as silicongermanium, indium antimonide, lead telluride compound, indium arsenide,indium phosphide, gallium arsenide, or gallium antimonide.Alternatively, the substrate 100 may be a base substrate having anepitaxial layer formed thereon.

The substrate 100 may be formed with a protrusion that forms thefin-type pattern 110. For example, the fin-type pattern 110 may protrudefrom a surface of the substrate 100. A field insulating layer 105 may atleast partially cover a sidewall of the fin-type pattern 110. Thefin-type pattern 110 may be defined by the field insulating layer 105.The field insulating layer 105 may include, for example, at least one ofan oxide layer, a nitride layer, an oxynitride layer or a combinationthereof.

Although the sidewall of the fin-type pattern 110 may be completelycovered by the field insulating layer 105 as shown in FIG. 1, this isonly for illustrative purpose, and it is not limited thereto. In someembodiments, the sidewall of the fin-type pattern 110 may be partiallycovered by the field insulating layer 105.

The fin-type pattern 110 may extend in a first direction X. For example,the fin-type pattern 110 may include a longer side extending in thefirst direction X, and a shorter side extending in a second direction Y.

The fin-type pattern 110 may be formed by partially etching thesubstrate 100. Alternatively, first fin-type pattern 110 may include anepitaxial layer grown on the substrate 100. The fin-type pattern 110 mayinclude an element semiconductor material such as silicon or germanium.Furthermore, the fin-type pattern 110 may include a compoundsemiconductor such as, IV-IV group compound semiconductor or III-V groupcompound semiconductor.

For example, in IV-IV group compound semiconductor, the fin-type pattern110 may be a binary compound or a ternary compound including, forexample, at least two or more of carbon (C), silicon (Si), germanium(Ge), and tin (Sn), or the above-mentioned binary or ternary compounddoped with IV group element.

For example, in III-V group compound semiconductor, the fin-type pattern110 may be a binary compound, ternary compound or quaternary compoundwhich is formed by combining at least one of aluminum (Al), gallium(Ga), and indium (In) from group III with at least one of phosphorus(P), arsenic (As), and antimony (Sb) from group V.

In the following description, it is assumed that the fin-type pattern110 includes silicon.

The first nanowire 120 may be formed on the substrate 100, and spacedapart from the substrate 100. The first nanowire 120 may extend in thefirst direction X.

The first nanowire 120 may be formed on the fin-type pattern 110, andspaced apart from the fin-type pattern 110. The first nanowire 120 maybe overlapped with the fin-type pattern 110. In some embodiments, thefirst nanowire 120 may be formed on the fin-type pattern 120, ratherthan being formed on the field insulating layer 105.

Although a width of the first nanowire 120 in the second direction Y maybe the same as a width of the fin-type pattern 110 in the seconddirection Y as shown in FIG. 4, this is only for illustrative purpose,and it is not limited thereto. Furthermore, although it is illustratedthat the first nanowire 120 has a square cross section, it is notlimited thereto. In some embodiments, the corner of the first nanowire120 may be rounded by a process such as trimming.

The first nanowire 120 may be used as a channel region for a transistor.A material of the first nanowire 120 may vary depending on whether thesemiconductor device is a PMOS or NMOS, but the disclosure is notlimited thereto.

The first nanowire 120 may include the same material as that of thefin-type pattern 110, or include a material different from that of thefin-type pattern 110. For convenience of explanation, in the followingdescription it will be assumed that the first nanowire 120 of thesemiconductor device includes silicon.

The gate electrode 130 may be formed on the field insulating layer 105and the fin-type pattern 110. The gate electrode 130 may extend in thesecond direction Y.

The gate electrode 130 may be so formed as to surround a periphery ofthe first nanowire 120 which is spaced apart from a top surface of thefin-type pattern 110. The gate electrode 130 may be also formed in aspace defined between the first nanowire 120 and the fin-type pattern110.

The gate electrode 130 may include a conductive material. Asillustrated, the gate electrode 130 may be a single layer, but thedisclosure is not limited thereto. For example, the gate electrode 130may include a work function conductive layer which adjusts a workfunction, and a filling conductive layer which fills a space formed bythe work function conductive layer.

The gate electrode 130 may include at least one of TiN, WN, TaN, Ru,TiC, TaC, Ti, Ag, Al, TiAl, TiAlN, TiAlC, TaCN, TaSiN, Mn, Zr, W, andAl. Alternatively, the gate electrode 130 may each be formed ofnon-metal element such as Si or SiGe. The gate electrode 130 describedabove may be formed by a replacement process, but the disclosure is notlimited thereto.

The gate spacer 140 may be formed on both (e.g., opposite) sidewalls ofthe gate electrode 130 which extends in the second direction Y. The gatespacer 140 may be formed on both sides of the first nanowire 120, tohave portions facing each other. The gate spacer 140 may include athrough hole 140 h. The first nanowire 120 may include opposite firstand second side surfaces. Accordingly, the gate spacer 140 may include afirst gate spacer 140 a which is in contact with the first side surface,and a second gate spacer 140 b which is in contact with the second sidesurface. The gate spacer 140 may be described herein as a single gatespacer having portions, which may be referred to as first portions,second portions, third portions, etc. The different portions may alsoeach be referred to as a gate spacer.

The first nanowire 120 may pass through the gate spacer 140. The firstnanowire 120 may pass through the through hole 140 h. The gate spacer140 may completely surround a periphery of a portion of side surfaces ofthe first nanowire 120.

When a corner of the first nanowire 120, which is surrounded by the gateelectrode, is rounded by the process such as trimming, a cross sectionof the first nanowire 120 in contact with the gate spacer 140 may bedifferent from a cross section of the first nanowire 120 surrounded bythe gate electrode 130.

The first gate spacer 140 a may include a first outer spacer 141 a and aportion of an inner spacer 142. The portion of the inner spacer 142 thatis included in the first gate spacer 140 a may also be referred to as afirst inner spacer. The first outer spacer 141 a may be in contact withthe inner spacer 142. The inner spacer 142 may be disposed between thetop surface of the fin-type pattern 110 and the first nanowire 120, andmay be in surface contact with the top surface of the fin-type pattern110. On an YZ cross section, the inner spacer 142 may be surrounded bythe first nanowire 120, the first outer spacer 141 a and the fin-typepattern 110.

The second gate spacer 140 b may include a second outer spacer 141 b anda portion of the inner spacer 142. The portion of the inner spacer 142that is included in the second gate spacer 140 b may also be referred toas a second inner spacer. The second outer spacer 141 b may be incontact with the inner spacer 142. The inner spacer 142 may be disposedbetween the top surface of the fin-type pattern 110 and the firstnanowire 120, and may be in surface contact with the top surface of thefin-type pattern 110. On an YZ cross section, the inner spacer 142 maybe surrounded by the first nanowire 120, the second outer spacer 141 band the fin-type pattern 110.

The first gate spacer 140 a and the second gate spacer 140 b may havethe same shape and material as each other. Hereinafter, the shape of thefirst gate spacer 140 a will be described by way of example embodiments.

The through hole 140 h of the first gate spacer 140 a may be defined bythe first outer spacer 141 a and the inner spacer 142. An end portion ofthe first nanowire 120 may be in contact with the first outer spacer 141a and the inner spacer 142.

Referring to FIG. 6, the through hole 140 h may include two first sides140 h-1 facing each other in the second direction Y, and two secondsides 140 h-2 facing each other in a third direction Z. The second sides140 h-2 of the through hole 140 h may connect the first sides 140 h-1 ofthe through hole 140 h which are facing each other.

In the semiconductor device according to example embodiments, at leastone of the second sides 140 h-2 of the through hole 140 h may be definedby the inner spacer 142. The first sides 140 h-1 of the through hole 140h may be defined by the first outer spacer 141 a.

More specifically, the through hole 140 h may include the three sides,e.g., the two first sides 140 h-1 and one of the second sides 140 h-2defined by the first outer spacer 141 a, and the one side, e.g., theother one of the second sides 140 h-2 defined by the inner spacer 142.

For example, the first sides 140 h-1 of the through hole 140 h may bedefined by the first outer spacer 141 a. Furthermore, one of the secondsides 140 h-2 of the through hole 140 h may be defined by the firstouter spacer 141 a, and the other second side 140 h-2 of the throughhole 140 h may be defined by the inner spacer 142.

The first outer spacer 141 a and the inner spacer 142 may includedifferent materials from each other. When a material included in thefirst outer spacer 141 a has a first dielectric constant, and a materialincluded in the inner spacer 142 has a second dielectric constant, thefirst and second dielectric constants may be different from each other.

In the semiconductor device according to example embodiments, thematerial included in the first outer spacer 141 a may have a greaterdielectric constant than the material included in the inner spacer 142.It is possible to reduce the fringing capacitance between the gateelectrode 130 and the source/drain 150 by having the second dielectricconstant lower than the first dielectric constant.

For example, the first outer spacer 141 a may include at least one ofsilicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO₂),silicon oxycarbidenitride (SiOCN), and a combination thereof. Forexample, the inner spacer 142 may include at least one of a low-kdielectric material, silicon nitride (SiN), silicon oxynitride (SiON),silicon oxide (SiO₂), silicon oxycarbidenitride (SiOCN), and acombination thereof. However, as mentioned earlier, according to exampleembodiments, the material included in the first outer spacer 141 a mayhave a greater dielectric constant than the material included in theinner spacer 142. The low-k dielectric material may be a material thathas a lower dielectric constant than silicon oxide.

The first outer spacer 141 a of the first gate spacer 140 a may includea first region 141 a-1 and a second region 141 a-2. The second region141 a-2 may be disposed on both sides of the first region 141 a-1 in thesecond direction Y.

The first region 141 a-1 may be a region where the first nanowire 120 ispassed through. The second region 141 a-2 may be a region where thefirst nanowire 120 need not pass through. For example, the through hole140 h of the gate spacer 140 a may be included in the first region 141a-1. More specifically, the through hole 140 h may be surrounded by thefirst region 141 a-1 and the inner spacer 142.

The second region 141 a-2 may include the first outer spacer 141 a only.Meanwhile, the first region 141 a-1 may include the first outer spacer141 a and the inner spacer 142. More specifically, the first region 141a-1 may include a portion of the first outer spacer 141 a.

A height from a top surface of the substrate 100 to the first region 141a-1 of the gate spacer may be greater than a height from the top surfaceof the substrate 100 to the inner spacer 142. At least one of the secondsides 140 h-2 of the through hole 140 h may be defined by the innerspacer 142. The first sides 140 h-1 of the through hole 140 h may bedefined by the first outer spacer 141 a.

The inner spacer 142 may be in contact with the second region 141 a-2.Furthermore, the second region 141 a-2 and the first region 141 a-1 maybe included in the first outer spacer 141 a. Accordingly, the secondregion 141 a-2 and the first region 141 a-1 may be an integralstructure.

There may be no layer between an uppermost portion of the first nanowire120 and the first outer spacer 141 a, for example, at an overlappingportion between the first gate spacer 140 a and the first nanowire 120.In other words, the uppermost portion of the first nanowire 120 may bein contact with the first region 140 a-1 of the gate spacer 140.

Accordingly, a lowermost portion of the first nanowire 120 may be incontact with the inner spacer 142 of the gate spacer 140, and theuppermost portion of the first nanowire 120 may be in contact with thefirst region 140 a-1 of the gate spacer 140.

Referring to FIGS. 2 and 3, the inner spacer 142 may include a spacedportion 142 c, a first protruding portion 142 a and a second protrudingportion 142 b.

The spaced portion 142 c may be formed to be spaced apart from the firstnanowire 120. A lower surface of the spaced portion 142 c may be incontact with the top surface of the fin-type pattern 110. For example,the lower surface of the spaced portion 142 c may be formed along thetop surface of the fin-type pattern 110.

The protruding portions 142 a and 142 b may extend from the spacedportion 142 c. The first protruding portion 142 a and the secondprotruding portion 142 b may be connected to both ends of the spacedportion 142 c. Accordingly, the gate electrode 130 may be formed betweenthe first protruding portion 142 a and the second protruding portion 142b. For example, the first protruding portion 142 a and the secondprotruding portion 142 b may each be formed on both sides of the gateelectrode 130.

The first protruding portion 142 a may be vertically overlapped with thefirst outer spacer 141 a. A width of the first protruding portion 142 amay be the same as that of the first outer spacer 141 a. But thedisclosure is not limited thereto.

Similarly, the second protruding portion 142 b may vertically overlapthe second outer spacer 141 b. A width of the second protruding portion142 b may be the same as that of the second outer spacer 141 b. But thedisclosure is not limited thereto.

The first gate spacer 140 a may include the first outer spacer 141 a andthe first protruding portion 142 a of the inner spacer 142. Similarly,the second gate spacer 140 b may include the second outer spacer 141 band the second protruding portion 142 b of the inner spacer 142. Thespaced portion 142 c of the inner spacer 142 may be a spacer connectorwhich connects the first gate spacer 140 a to the second gate spacer 140b. For example, the first gate spacer 140 a and the second gate spacer140 b formed opposite to each other around the gate electrode 130 may beconnected to each other by the spaced portion 142 c (i.e., the spacerconnector) of the inner spacer 142.

In some embodiments, the inner spacer 142 may not include the protrudingportions 142 a and 142 b. In this case, a top surface of the innerspacer 142 may be completely in contact with a lower surface of thefirst nanowire 120. For example, the inner spacer 142 may have the flattop surface, and extend in the first direction X.

The gate insulating layer 147 may be formed between the first nanowire120 and the gate electrode 130. Furthermore, the gate insulating layer147 may be formed between the field insulating layer 105 and the gateelectrode 130, and between the inner spacer 142 and the gate electrode130.

For example, the gate insulating layer 147 may include an interfacelayer 146 and a high-k insulating layer 145, but the disclosure is notlimited thereto. For example, the interface layer 146 of the gateinsulating layer 147 may be omitted depending on a material for thefirst nanowire 120.

Because the interface layer 146 may be formed on a periphery of thefirst nanowire 120, the interface layer 146 may be formed between thefirst nanowire 120 and the gate electrode 130, and between the fin-typepattern 110 and the gate electrode 130. Meanwhile, the high-k insulatinglayer 145 may be formed between the first nanowire 120 and the gateelectrode 130, between the inner spacer 142 and the gate electrode 130,between the field insulating layer 105 and the gate electrode 130, andbetween the outer spacer 141 and the gate electrode 130.

The gate insulating layer 147 may be formed along the periphery of thefirst nanowire 120. The gate insulating layer 147 may be formed along atop surface of the field insulating layer 105, and a top surface of thespaced portion 142 c of the inner spacer 142. In addition, the gateinsulating layer 147 may be formed along sidewalls of the inner spacer142 and the outer spacer 141.

When the first nanowire 120 includes silicon, the interface layer 146may include a silicon oxide layer. In this embodiment, when theinterface layer 146 includes a silicon oxide layer, the interface layer146 may be formed on the periphery of the first nanowire 120 and the topsurface of the inner spacer 142, but need not be formed along thesidewalls of the inner spacer 142 and the outer spacer 141.

The high-k insulating layer 145 may include a high-k dielectric materialhaving a higher dielectric constant than a silicon oxide layer. Forexample, the high-k dielectric material may include at least one ofhafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanumaluminum oxide, zirconium oxide, zirconium silicon oxide, tantalumoxide, titanium oxide, barium strontium titanium oxide, barium titaniumoxide, strontium titanium oxide, yttrium oxide, aluminum oxide, leadscandium tantalum oxide, and lead zinc niobate, but the disclosure isnot limited thereto.

As described above, when the interface layer 146 is omitted, the high-kinsulating layer 145 may include not only the high-k dielectricmaterial, but also silicon oxide layer, silicon oxynitride layer, orsilicon nitride layer.

In some embodiments, the source/drain 150 may be formed on both sides ofthe gate electrode 130. The source/drain 150 may be formed on thefin-type pattern 110. The source/drain 150 may include an epitaxiallayer formed on the top surface of the fin-type pattern 110.

An outer circumference of the source/drain 150 may have a variety ofshapes. For example, the outer circumference of the source/drain 150 maybe at least one of diamond, circle, rectangle, and octagon shapes. FIG.1 illustrates a diamond shape (or pentagon or hexagon shape), for anexample.

The source/drain 150 may be directly connected with the first nanowire120 which is used as the channel region. For example, the source/drain150 may be directly connected with the first nanowire 120 which ispassed through the through hole 140 h of the gate spacer 140.

However, the source/drain 150 need not be in contact with the gateinsulating layer 147. The gate spacer 140 may be located between thesource/drain 150 and the gate insulating layer 147. For example, onesidewall of the inner spacer 142 may be in contact with the gateinsulating layer 147, while the other sidewall of the inner spacer 142may be in contact with the source/drain 150, in which case thesource/drain 150 and the gate insulating layer 147 need not contact eachother between the first nanowire 120 and the substrate 100. Furthermore,since the outer spacer 141 is in contact with the uppermost portion ofthe first nanowire 120, the source/drain 150 and the gate insulatinglayer 147 need not contact each other over the first nanowire 120.

Hereinafter, a semiconductor device according to another exampleembodiment of the inventive concept will be explained with reference toFIGS. 1 and 7 to 9. For convenience of explanation, differences that arenot explained above with reference to FIGS. 1 to 6 will be mainlyexplained below.

FIG. 7 is a cross-sectional view illustrating a semiconductor deviceaccording to some exemplary embodiments of the inventive concept. FIG. 8is a cross-sectional view illustrating the semiconductor device of FIG.7. FIG. 9 is a cross-sectional view illustrating an inner spacer and anouter spacer of FIG. 8 in detail.

For reference, FIG. 7 is a cross-sectional view taken along line A-A′ ofFIG. 1. FIG. 8 is a cross-sectional view taken along line C-C′ ofFIG. 1. FIG. 9 illustrates only the gate spacer of FIG. 7.

Referring to FIGS. 1 and 7 to 9, a semiconductor device according tosome embodiments may include a lower inner spacer 142 and an upper innerspacer 142-1 which is spaced apart from the lower inner spacer 142 in athird direction Z. The upper inner spacer 142-1 may include a firstupper inner spacer 142-1 a which is contacted with the first sidewall ofthe gate electrode 130 and a second upper inner spacer 142-1 b which iscontacted with the second sidewall of the gate electrode 130 opposite tothe first sidewall of the gate electrode 130.

Accordingly, the uppermost portion of the first nanowire 120 may be incontact with the upper inner spacer 142-1, and the lowermost portion ofthe first nanowire 120 may be in contact with the lower inner spacer142.

In the first region 141 a-1, the lower inner spacer 142 and the firstupper inner spacer 142-1 a may be disposed over and under the firstnanowire 120, respectively. The lower inner spacer 142 and the firstupper inner spacer 142-1 a may include a material having a lowerdielectric constant than the first outer spacer 141 a.

The through hole 140 h may include two sides 140 h-1 which are definedby the first outer spacer 141 a, and two sides 140 h-2 which are definedby the lower inner spacer 142 and the first upper inner spacer 142-1 a.

In some embodiments, first sides 140 h-1 of the through hole 140 hfacing each other in the second direction Y may be defined by the firstouter spacer 141 a, and second sides 140 h-2 of the through hole 140 hfacing each other in the third direction Z may be defined by the lowerinner spacer 142 and the first upper inner spacer 142-1 a.

The second gate spacer 140 b is substantially the same shape as that ofthe first gate spacer 140 a, so a detailed description thereof isomitted and replaced by the description of the first gate spacer 140 a.

A semiconductor device according to still another exemplary embodimentof the inventive concept will be explained with reference to FIGS. 1 and10 to 12. For convenience of explanation, differences that are notexplained above with reference to FIGS. 1 to 9 will be mainly explainedbelow.

FIGS. 10 to 12 are cross-sectional views illustrating a semiconductordevice according to some example embodiments of the inventive concept.

FIG. 10 is a cross-sectional view taken along line A-A′ of FIG. 1. FIG.11 is a cross-sectional view taken along line B-B′ of FIG. 1. FIG. 12 isa cross-sectional view taken along line C-C′ of FIG. 1.

Referring to FIGS. 1 and 10 to 12, a semiconductor device according tosome example embodiments of the inventive concept may further include asecond nanowire 125.

The second nanowire 125 may be formed on the substrate 100, while beingspaced apart from the substrate 100. The second nanowire 125 may extendin the first direction X.

The second nanowire 125 may be spaced apart from the substrate 100further than the first nanowire 120. For example, a height from the topsurface of the fin-type pattern 110 to the second nanowire 125 may begreater than a height from the top surface of the fin-type pattern 110to the first nanowire 120. More specifically, in some embodiments, aheight from the uppermost surface of the fin-type pattern 110 (or theuppermost surface of the substrate 100) to the lowermost surface of thesecond nanowire 125 may be greater than a height from the uppermostsurface of the fin-type pattern 110 (or the uppermost surface of thesubstrate 100) to the lowermost surface of the first nanowire 120. Insome embodiments, a height from the uppermost surface of the fin-typepattern 110 (or the uppermost surface of the substrate 100) to theuppermost surface of the second nanowire 125 may be greater than aheight from the uppermost surface of the fin-type pattern 110 (or theuppermost surface of the substrate 100) to the uppermost surface of thefirst nanowire 120.

The second nanowire 125 may be overlapped with the fin-type pattern 110.The second nanowire 125 may be formed on the fin-type pattern 110,rather than being formed on the field insulating layer 105.

The second nanowire 125 may be used as a channel region for thetransistor. Accordingly, the second nanowire 125 may include the samematerial as the first nanowire 120.

The gate electrode 130 may be formed to surround the periphery of thesecond nanowire 125. The gate electrode 130 may be also formed in thespace defined between the first nanowire 120 and the second nanowire125.

The gate spacer 140 may be disposed on both ends of the first nanowire120 and on both ends of the second nanowire 125. The gate spacer 140 mayeach include a plurality of through holes 140 h.

The second nanowire 125 may pass through the gate spacer 140. The secondnanowire 125 may pass through one of the plurality of through holes 140h. The periphery of the end of the second nanowire 125 may be contactedwith the gate spacer 140.

Like the first nanowire 120, when the corner of the second nanowire 125,which is surrounded by the gate electrode 130, is rounded by the processsuch as trimming, the end of the second nanowire 125 in contact with thegate spacer 140 may have a different cross section than a cross sectionof the second nanowire 125 surrounded by the gate electrode 130.

The second nanowire 125 may be aligned with the first nanowire 120. Thesecond nanowire 125 may be overlapped with the first nanowire 120 in thethird direction Z. The first nanowire 120 and the second nanowire 125may have the same length as each other. But the disclosure is notlimited thereto.

The lower inner spacer 142 may be disposed between the top surface ofthe fin-type pattern 110 and the first nanowire 120. The first upperinner spacer 142-1 may be disposed between the first nanowire 120 andthe second nanowire 125.

Referring to FIG. 10, the uppermost surface of the second nanowire 125may be in contact with the outer spacer 141, and the lowermost surfaceof the second nanowire 125 may be in contact with the first upper innerspacer 142-1.

The gate insulating layer 147 may be formed between the second nanowire125 and the gate electrode 130. The gate insulating layer 147 may beformed along the periphery of the second nanowire 125.

The source/drain 150 may be directly connected to the second nanowire125 which is used as the channel region. For example, the source/drain150 may be directly connected to the first nanowire 120 and the secondnanowire 125 which are passed through the through holes 140 h of thegate spacer 140.

Hereinafter, a semiconductor device according to still another exemplaryembodiment of the inventive concept will be explained with reference toFIGS. 1 and 13 to 15. For convenience of explanation, differences thatare not explained above with reference to FIGS. 1 to 12 will be mainlyexplained below.

FIGS. 13 to 15 are cross-sectional views illustrating a semiconductordevice according to some example embodiments of the inventive concept.

FIG. 13 is a cross-sectional view taken along line A-A′ of FIG. 1. FIG.14 is a cross-sectional view taken along line B-B′ of FIG. 1. FIG. 15 isa cross-sectional view taken along line C-C′ of FIG. 1.

Referring to FIGS. 1 and 13 to 15, a semiconductor device according tosome example embodiments of the inventive concept may further include athird nanowire 127 and a second upper inner spacer 142-2.

The third nanowire 127 may be formed on the substrate 100, while beingspaced apart from the substrate 100. The third nanowire 127 may extendin the first direction X.

The third nanowire 127 may be spaced apart from the substrate 100further than the first nanowire 110 and the second nanowire 125. Forexample, a height from the top surface of the fin-type pattern 110 tothe third nanowire 127 may be greater than a height from the top surfaceof the fin-type pattern 110 to the first nanowire 120 or second nanowire125. More specifically, in some embodiments, a height from the uppermostsurface of the fin-type pattern 110 (or the uppermost surface of thesubstrate 100) to the lowermost surface of the third nanowire 127 may begreater than a height from the uppermost surface of the fin-type pattern110 (or the uppermost surface of the substrate 100) to the lowermostsurface of the first nanowire 120 or the lowermost surface of the secondnanowire 125. In some embodiments, a height from the uppermost surfaceof the fin-type pattern 110 (or the uppermost surface of the substrate100) to the uppermost surface of the third nanowire 127 may be greaterthan a height from the uppermost surface of the fin-type pattern 110 (orthe uppermost surface of the substrate 100) to the uppermost surface ofthe first nanowire 120 or the uppermost surface of the second nanowire125.

The third nanowire 127 may be overlapped with the fin-type pattern 110.In some embodiments, the third nanowire 127 may be formed on thefin-type pattern 110, rather than being formed on the field insulatinglayer 105.

The third nanowire 127 may be used as a channel region for thetransistor. Accordingly, the third nanowire 127 may include the samematerial as the first nanowire 120 and the second nanowire 125.

The gate electrode 130 may be formed to surround the periphery of thethird nanowire 127. The gate electrode 130 may be also formed in thespace defined between the second nanowire 125 and the third nanowire127.

The gate spacer 140 may be disposed on both ends of the first nanowire120, on both ends of the second nanowire 125, and on both ends of thethird nanowire 127. The gate spacer 140 may each include a plurality ofthrough holes 140 h.

The third nanowire 127 may pass through the gate spacer 140. The thirdnanowire 127 may pass through one of the plurality of through holes 140h. The periphery of the end of the third nanowire 127 may be completelycontacted with the gate spacer 140.

Like the first nanowire 120 and the second nanowire 125, when the cornerof the third nanowire 127, which is surrounded by the gate electrode130, is rounded by the process such as trimming, the end of the thirdnanowire 127 in contact with the gate spacer 140 may have a differentcross section than a cross section of the third nanowire 127 surroundedby the gate electrode 130.

The third nanowire 127 may be aligned with the first nanowire 120 andthe second nanowire 125. The third nanowire 127 may be overlapped withthe first nanowire 120 and the second nanowire 125 in the thirddirection Z. In some embodiments, the first to third nanowires 120, 125and 127 may have the same length as each other. But the disclosure isnot limited thereto.

The lower inner spacer 142 may be disposed between the top surface ofthe fin-type pattern 110 and the first nanowire 120. The first upperinner spacer 142-1 may be disposed between the first nanowire 120 andthe second nanowire 125. The second upper inner spacer 142-2 may bedisposed between the second nanowire 125 and the third nanowire 127. Thesecond upper inner spacer 142-2 may include a second upper inner spacer142-2 a which is contacted with the first sidewall of the gate electrode130, and a second upper inner spacer 142-2 b which is contacted with thesecond sidewall of the gate electrode 130.

Referring to FIG. 13, the uppermost surface of the third nanowire 127may be in contact with the outer spacer 141, and the lowermost surfaceof the third nanowire 127 may be in contact with the second upper innerspacer 142-2. But the disclosure is not limited thereto.

The gate insulating layer 147 may be formed between the third nanowire127 and the gate electrode 130. The gate insulating layer 147 may beformed along the periphery of the third nanowire 127.

The source/drain 150 may be directly connected to the third nanowire 127which is used as the channel region. For example, the source/drain 150may be directly connected to the first to third nanowires 120, 125 and127 which are passed through the through holes 140 h of the gate spacer140.

Hereinafter, a semiconductor device according to still another exemplaryembodiment of the inventive concept will be explained with reference toFIGS. 1 and 16 to 18. For convenience of explanation, differences thatare not explained above with reference to FIGS. 1 to 15 will be mainlyexplained below.

FIGS. 16 to 18 are cross-sectional views illustrating a semiconductordevice according to some example embodiments of the inventive concept.

FIG. 16 is a cross-sectional view taken along line A-A′ of FIG. 1. FIG.17 is a cross-sectional view taken along line B-B′ of FIG. 1. FIG. 18 isa cross-sectional view taken along line C-C′ of FIG. 1.

Referring to FIGS. 1 and 16 to 18, a semiconductor device according tosome example embodiments of the inventive concept may include apassivation layer 119.

The passivation layer 119 may be formed for preventing a loss of thefirst nanowire 120 during the etching process. The passivation layer 119may be formed between the top surfaces of the protruding portions 142 aand 142 b of the lower inner spacer 142 and the lower surface of thefirst nanowire 120.

The passivation layer 119 may include a first passivation layer 119 aand a second passivation layer 119 b. The first passivation layer 119 amay be formed on the first protruding portion 142 a. The secondpassivation layer 119 a may be formed on the second protruding portion142 b.

A width of the first passivation layer 119 a may be the same as that ofthe first protruding portion 142 a. A width of the second passivationlayer 119 b may be the same as that of the second protruding portion 142b. The passivation layer 119 may include silicon.

Hereinafter, a method for fabricating a semiconductor device accordingto example embodiments of the inventive concept will be explained withreference to FIGS. 19 to 36. The semiconductor device fabricated basedFIGS. 19 to 36 corresponds to the semiconductor device described abovewith reference to FIGS. 7 to 9.

FIGS. 19 to 36 are drawings illustrating a method for fabricating asemiconductor device according to example embodiments of the inventiveconcept. FIGS. 31, 33 and 35 are cross-sectional views taken along lineD-D′ of FIG. 30. FIGS. 32, 34 and 36 are cross-sectional views takenalong line E-E′ of FIG. 30.

Referring to FIG. 19, a lower sacrificial layer 2005, a firstsacrificial layer 2001, a free passivation layer 2004, an active layer2002 and a second sacrificial layer 2003 may be sequentially formed onthe substrate 100.

The first sacrificial layer 2001 and the second sacrificial layer 2003may include the same material, and the first sacrificial layer 2001 andthe active layer 2002 may include different materials. In explaining amethod for fabricating a semiconductor device according to an exampleembodiment, it is assumed that the first sacrificial layer 2001 and thesecond sacrificial layer 2003 include the same material. Furthermore,the active layer 2002 may include a material with an etch selectivitywith respect to the first sacrificial layer 2001.

The lower sacrificial layer 2005 may include the same material as thefirst sacrificial layer 2001 and the second sacrificial layer 2003, butthey may be doped with different materials with the dopingconcentrations.

For example, the substrate 100 and the active layer 2002 may include amaterial used as a channel region for the transistor. In the case ofPMOS transistors, the active layer 2002 may include a material with highhole mobility, while in the case of NMOS transistors, the active layer2002 may include a material with high electron mobility.

The first sacrificial layer 2001 and the second sacrificial layer 2003may include a material having a similar lattice constant and latticestructure as the active layer 2002. For example, the first sacrificiallayer 2001 and the second sacrificial layer 2003 may be a semiconductormaterial or a crystallized metal material.

In explaining a method for fabricating a semiconductor device accordingto an example embodiment, it is assumed that the active layer 2002includes silicon, and the first sacrificial layer 2001 and the secondsacrificial layer 2003 each include silicon germanium. Furthermore, thelower sacrificial layer 2005 may also include silicon germanium.

A germanium concentration of the lower sacrificial layer 2005 may begreater than that of each of the first sacrificial layer 2001 and secondsacrificial layer 2003. Through this, an etching rate of the lowersacrificial layer 2005 may be markedly increased compared to an etchingrate of each of the first sacrificial layer 2001 and the secondsacrificial layer 2003 during the etching process.

FIG. 19 illustrates only one active layer 2002, but this is only forconvenience of explanation and the example embodiments are not limitedthereto. For example, there may be plural pairs of the first sacrificiallayer 2001 and the active layer 2002 formed in turn, with the secondsacrificial layer 2003 being formed on the uppermost active layer 2002.

Furthermore, although FIG. 19 illustrates the second sacrificial layer2003 positioned on the uppermost portion of the stack layer structure,the example embodiments are not limited thereto. For example, the activelayer 2002 may be on the uppermost portion of the stack layer structure.

Next, a first mask pattern 2103 may be formed on the second sacrificiallayer 2003. The first mask pattern 2103 may extend in the firstdirection X.

The first mask pattern 2103 may be formed of a material including atleast one of, for example, a silicon oxide layer, a silicon nitridelayer and a silicon oxynitride layer.

Referring to FIG. 20, an etching process may be performed using thefirst mask pattern 2103 as an etch mask to form a fin-type structure110P.

The fin-type structure 110P may be formed by patterning portions of thesecond sacrificial layer 2003, the active layer 2002, the freepassivation layer 2004, the first sacrificial layer 2001, the lowersacrificial layer 2005 and the substrate 100.

The fin-type structure 110P may be formed on the substrate 100, andprotruded from the substrate 100. The fin-type structure 110P may extendin the first direction X, like in the case of the first mask pattern2103.

In the fin-type structure 110P, a fin-type pattern 110, a lowersacrificial pattern 124, a first sacrificial pattern 121, a passivationlayer 119, a first nanowire 120 and a second sacrificial pattern 123 maybe sequentially stacked on the substrate 100.

Referring to FIG. 21, a field insulating layer 105 may be formed on thesubstrate 100 to cover at least a portion of sidewalls of the fin-typestructure 110P.

For example, the field insulating layer 105 may be formed on thesubstrate 100 to cover the fin-type structure 110P. By performing aplanarization process for the field insulating layer 105, a top surfaceof the fin-type structure 110P and a top surface of the field insulatinglayer 105 may be placed on the same plane.

The first mask pattern 2103 may be removed in the planarization process,but the disclosure is not limited thereto.

An upper portion of the field insulating layer 105 may be then recessedto expose a portion of the fin-type structure 110P. The recess processmay include a selective etching process. Accordingly, the fin-typestructure may be formed to protrude on the field insulating layer 105.

Referring to FIG. 21, the second sacrificial pattern 123, the firstnanowire 120, the passivation layer 119, the first sacrificial pattern121 and the lower sacrificial pattern 124 may protrude on the topsurface of the field insulating layer 105, and the sidewall of thefin-type pattern 110 may be surrounded by the field insulating layer105. But the disclosure is not limited thereto. For example, a portionof the sidewall of the fin-type pattern 110 may protrude on the topsurface of the field insulating layer 105 through the recessing processof the upper portion of the field insulating layer 105.

The first nanowire 120 may be doped with impurities to adjust athreshold voltage of a transistor, before and/or after the recessingprocess which causes the portion of the fin-type structure 110P toprotrude beyond the top surface of the field insulating layer 105. Whenthe semiconductor device is an NMOS transistor, the impurity may beboron (B). When the semiconductor device is a PMOS transistor, theimpurity may be phosphorus (P) or arsenic (As). But the disclosure isnot limited thereto.

Referring to FIG. 22, a dummy gate pattern 135 may be formed byperforming the etching process using a second mask pattern 2104 as anetch mask. The dummy gate pattern 135 may cross the fin-type structure110P, and extend in the second direction Y. The dummy gate pattern 135may be formed on the fin-type structure 110P.

The dummy gate pattern 135 may include a dummy gate insulating layer 136and a dummy gate electrode 137. For example, the dummy gate insulatinglayer 136 may include a silicon oxide layer, and the dummy gateelectrode 137 may include polysilicon or amorphous silicon.

Referring to FIG. 23, an outer spacer 141 may be formed on the sidewallsof the dummy gate insulating layer 136 and the dummy gate electrode 137.

For example, a first spacer layer may be formed on the field insulatinglayer 105 to cover the dummy gate pattern 135 and the fin-type structure110P. The first spacer layer may be then etched-back to form the outerspacer 141 on the sidewalls of the dummy gate insulating layer 136 andthe dummy gate electrode 137.

Referring to FIG. 24, a portion of the fin-type structure 110P, which isnot overlapped with the dummy gate electrode 137 and the outer spacer141, may be removed using an etching process. In the etching process,the dummy gate pattern 135 may serve as an etch mask. By doing so, arecess 150 r may be formed within the fin-type structure 110P. A bottomsurface of the recess 150 r may be the top surface of the fin-typepattern 110.

Forming the outer spacer 141 and forming the recess 150 r may beconcurrently performed, but the disclosure is not limited thereto. Forexample, the recess 150 r may be formed by removing a portion of thefin-type structure 110P, after forming the outer spacer 141.

By the presence of the recess 150 r, a cross section of the lowersacrificial pattern 124, a cross section of the first sacrificialpattern 121, a cross section of the passivation layer 119, a crosssection of the second sacrificial pattern 123 and a cross section of thefirst nanowire 120 may be exposed.

Referring to FIG. 25, the entirety of the lower sacrificial pattern 124,at least a part of the first sacrificial layer 121 and at least a partof the second sacrificial pattern 123, which are exposed by the recess150 r, may be removed. Accordingly, a lower through hole 142 h may beformed between the outer spacers 141 and pass through the dummy gatepattern 135.

Furthermore, a first dimple 142 r 1 may be formed in at least a portionof the first sacrificial pattern 121 which is exposed by the recess 150r and overlapped with the outer spacer 141. A second dimple 142 r 2 maybe formed in at least a portion of the second sacrificial pattern 123which is exposed by the recess 150 r and overlapped between the outerspacer 141 and the first nanowire 120.

The first and second dimples 142 r 1 and 142 r 2 may be in the form of aconcave recess, and be more recessed in the first direction X than theend surface of the first nanowire 120.

For example, the dimples 142 r 1 and 142 r 2 may be formed by using aselective etching process. More specifically, the dimples 142 r 1 and142 r 2 may be formed by the etching process using an etchant with etchselectivity of the first sacrificial pattern 121 and the secondsacrificial pattern 123 with respect to the first nanowire 120.

For example, the lower through hole 142 h may be formed by using aselective etching process. More specifically, the lower through hole 142h may be formed by the etching process using an etchant with etchselectivity of the first nanowire 120, the first sacrificial pattern 121and the second sacrificial pattern 123 with respect to the lowersacrificial pattern 124.

Referring to FIG. 26, a portion of the passivation layer 119 may beremoved. The portion of the passivation layer 119, which is not coveredwith the first sacrificial pattern 121, may be only removed. Forexample, the portion of the passivation layer 119 exposed by the firstdimple 142 r 1 may be removed. Accordingly, the first dimple 142 r 1 maybe extended to a third dimple 142 r 1′.

In some embodiments, the passivation layer 119 may be not removed. Bydoing so, the semiconductor device shown in FIGS. 16 to 18 may befabricated.

Referring to FIG. 27, the third dimple 142 r 1′ may be filled with aninsulating material to form the lower inner spacer 142, and the seconddimple 142 r 2 may be filled with the insulating material to form thefirst upper inner spacer 142-1.

For example, a second spacer layer filling the dimples 142 r 1′ and 142r 2 may be formed on the substrate 100. The second spacer layer may be amaterial with a good gap-filling capability. The second spacer layer mayalso be formed on the field insulating layer 105, the sidewall of theouter spacer 141 and the dummy gate pattern 135.

An etching process may then be performed to etch the second spacer layeruntil the top surface of the fin-type pattern 110, which is notoverlapped with the dummy gate pattern 135 and the outer spacer 141, isexposed. As a result, the lower inner spacer 142 and the first upperinner spacer 142-1 may be formed.

Accordingly, the gate spacer 140 including the outer spacer 141, thelower inner spacer 142 and the first upper inner spacer 142-1 may beformed.

Furthermore, the through hole 140 h may be defined by the outer spacer141, the lower inner spacer 142 and the first upper inner spacer 142-1.The first nanowire 120 may be exposed by the through hole 140 h. Forexample, the first nanowire 120 may pass through the through hole 140 h.

Referring to FIG. 28, a source/drain 150 for filling the recess 150 rmay be formed on the substrate 100. The source/drain 150 may be formedon both sides of the dummy gate pattern 135.

The source/drain 150 may be formed using the exposed fin-type pattern110 and the first nanowire 120 as a seed layer.

The source/drain 150 may be formed to cover the lower inner spacer 142.The source/drain 150 may be in contact with the lower inner spacer 142.

The source/drain 150 may be formed by an epitaxial process. Depending onwhether a semiconductor device according to example embodiment is ann-type transistor or a p-type transistor, impurities doped in theepitaxial layer of the source/drain 150 may vary. Impurities may bedoped in situ during epitaxial process.

Referring to FIG. 29, an interlayer insulating layer 180 may be formedon the field insulating layer 105 to cover the source/drain 150, thegate spacer 140, the dummy gate pattern 135, and so on.

The interlayer insulating layer 180 may include at least one of low-kdielectric material, oxide, nitride and oxynitride. For example, thelow-k dielectric material may be flowable oxide (FOX), Tonen SilaZen(TOSZ), undoped silica glass (USG), borosilica glass (BSG),phosphosilica glass (PSG), borophosphosilica glass (BPSG), plasmaenhanced tetra ethyl ortho silicate (PETEOS), fluoride silicate glass(FSG), high density plasma (HDP) oxide, plasma enhanced oxide (PEOX),flowable CVD (FCVD) oxide, or a combination thereof.

The interlayer insulating layer 180 may be then planarized until the topsurface of the dummy gate electrode 137 is exposed. As a result, thesecond mask pattern 2104 may be removed to expose the top surface of thedummy gate electrode 137.

Referring to FIGS. 30 to 32, the dummy gate pattern 135, i.e., the dummygate insulating layer 136 and the dummy gate electrode 137, may beremoved.

By removing the dummy gate insulating layer 136 and the dummy gateelectrode 137, the field insulating layer 105 and the fin-type structure110P overlapped with the dummy gate pattern 135 may be exposed. Forexample, the first sacrificial pattern 121, the second sacrificialpattern 123, the passivation layer 119 and the first nanowire 120 may beexposed.

Referring to FIGS. 33 and 34, the first sacrificial pattern 121 and thesecond sacrificial pattern 123 may be removed from the fin-typestructure 110P. As a result, a space may be formed between thepassivation layer 119 and the lower inner spacer 142, and the firstnanowire 120 may be exposed over the fin-type pattern 110.

Removing the first sacrificial pattern 121 and the second sacrificialpattern 123 over and under the first nanowire 120 may be performed by,for example, an etching process. For example, etch selectivity of thefirst sacrificial pattern 121 and the second sacrificial pattern 123with respect to the first nanowire 120 may be utilized.

Additionally, the removal of the first sacrificial pattern 121 and thesecond sacrificial pattern 123 may allow the protruding portions 142 aand 142 b of the lower inner spacer 142 to be exposed.

Referring to FIGS. 35 and 36, the passivation layer 119 may be removed.Accordingly, the lower surface of the first nanowire 120 may be exposed.

Referring back to FIG. 7, an interface layer 146 may be formed on aperiphery of the first nanowire 120 and the top surface of the fin-typepattern 110.

The high-k insulating layer 145 may then be formed on the sidewall ofthe gate spacer 140, i.e., on sidewalls of the outer spacer 141, thelower inner spacer 142 and the first upper inner spacer 142-1, and alongthe periphery of the first nanowire 120. Accordingly, the gateinsulating layer 147 including the interface layer 146 and the high-kinsulating layer 145 may be formed.

Next, the gate electrode 130 surrounding the first nanowire 120 andextending in the second direction Y may be formed. The gate electrode130 may be a replacement metal gate electrode.

FIG. 37 is a block diagram of an electronic system comprising asemiconductor device according to some example embodiments of theinventive concept.

Referring to FIG. 37, an electronic system 1100 according to an exampleembodiment may include a controller 1110, an input/output (I/O) device1120, a memory device 1130, an interface 1140 and a bus 1150. Thecontroller 1110, the I/O device 1120, the memory device 1130 and/or theinterface 1140 may be coupled with one another via the bus 1150. The bus1150 corresponds to a path through which data travels.

The controller 1110 may include at least one of a microprocessor, adigital signal processor, a micro controller and a logic device capableof performing functions similar to those mentioned above. The I/O device1120 may include a keypad, a keyboard, or a display device. The memorydevice 1130 may store data and/or commands. The interface 1140 mayperform a function of transmitting data to communication networks orreceiving data from the communication networks. The interface 1140 maybe wired or wireless. For example, the interface 1140 may include anantenna or a wired/wireless transceiver. Although not illustrated, theelectronic system 1100 may additionally include an operation memoryconfigured to enhance operation of the controller 1110, such as ahigh-speed dynamic random access memory (DRAM) and/or a static randomaccess memory (SRAM). According to an example embodiment, asemiconductor device fabricated according to an example embodiment maybe provided within the memory device 1130, or provided as a part of thecontroller 1110, or the I/O device 1120.

The electronic system 1100 is applicable to a personal digital assistant(PDA) portable computer, a web tablet, a wireless phone, a mobile phone,a digital music player, a memory card, or almost all electronic productsthat are capable of transmitting and/or receiving data in wirelessenvironment.

FIGS. 38 and 39 illustrate exemplary semiconductor system including asemiconductor device according to an example embodiment. FIG. 38illustrates a tablet PC and FIG. 39 illustrates a laptop computer. Asemiconductor device according to an example embodiment may be used inthe tablet PC or the laptop computer. A semiconductor device accordingto an example embodiment may be applicable to an integrated circuitdevice not illustrated herein.

While some embodiments of the inventive concepts have been particularlyshown and described, it will be understood by one of ordinary skill inthe art that variations in form and detail may be made therein withoutdeparting from the spirit and scope of the attached claims.

What is claimed is:
 1. A semiconductor device, comprising: a substrate;a first nanowire extended in a first direction and spaced apart from thesubstrate; a gate electrode surrounding a periphery of the firstnanowire, extending in a second direction intersecting the firstdirection, and comprising first and second sidewalls opposite to eachother; a first gate spacer formed on the first sidewall of the gateelectrode, wherein the first nanowire passes through the first gatespacer; a second gate spacer formed on the second sidewall of the gateelectrode, wherein the first nanowire passes through the second gatespacer; a source/drain disposed on at least one side of the gateelectrode and connected with the first nanowire; and a spacer connectordisposed between the first nanowire and the substrate, wherein thespacer connector connects the first gate spacer and the second gatespacer to each other.
 2. The semiconductor device of claim 1, whereinthe first gate spacer comprises a first outer spacer contacting top andside surfaces of the first nanowire, and a first inner spacer contactinga lower surface of the first nanowire, wherein the second gate spacercomprises a second outer spacer contacting the top and side surfaces ofthe first nanowire and a second inner spacer contacting the lowersurface of the first nanowire, wherein the first outer spacer and thefirst inner spacer comprise different materials from each other, andwherein the second outer spacer and the second inner spacer comprisedifferent materials from each other.
 3. The semiconductor device ofclaim 2, wherein the first and second inner spacers comprise the samematerial as each other.
 4. The semiconductor device of claim 2, whereinthe first and second outer spacers are spaced apart from each other,wherein the first and second inner spacers are connected to each otherthrough the spacer connector.
 5. The semiconductor device of claim 4,wherein the spacer connector and the first and second inner spacers area single integrated structure.
 6. The semiconductor device of claim 1,further comprising a second nanowire disposed on the first nanowire andextended in the first direction, wherein the first nanowire and thesecond nanowire are spaced apart from each other.
 7. The semiconductordevice of claim 6, wherein the first gate spacer comprises a first outerspacer contacting top and side surfaces of the second nanowire and aside surface of the first nanowire, a first upper inner spacercontacting a lower surface of the second nanowire and a top surface ofthe first nanowire, and a first lower inner spacer contacting a lowersurface of the first nanowire, and wherein the second gate spacercomprises a second outer spacer contacting the top and side surfaces ofthe second nanowire and the side surface of the first nanowire, a secondupper inner spacer contacting the lower surface of the second nanowireand the top surface of the first nanowire, and a second lower innerspacer contacting the lower surface of the first nanowire.
 8. Thesemiconductor device of claim 7, wherein the first upper inner spacerand the first lower inner spacer comprise the same material as eachother, and wherein the second upper inner spacer and the second lowerinner spacer comprise the same material as each other.
 9. Thesemiconductor device of claim 7, wherein the first lower inner spacerand the second lower inner spacer are connected to each other throughthe spacer connector.
 10. The semiconductor device of claim 1, whereinthe spacer connector comprises an insulating material.
 11. Asemiconductor device, comprising: a substrate; a first nanowire extendedin a first direction and spaced apart from the substrate; a gateelectrode surrounding a periphery of the first nanowire and extending ina second direction intersecting the first direction; a gate spacerdisposed on a sidewall of the gate electrode, wherein the gate spacercomprises inner and outer sidewalls opposite to each other, and theinner sidewall of the gate spacer faces the gate electrode; asource/drain disposed on at least one side of the gate electrode andconnected with the first nanowire, wherein the first nanowire passesthrough the gate spacer to be connected to the source/drain; and aninner spacer comprising a protruding portion disposed between thesubstrate and the first nanowire and contacting a lower surface of thefirst nanowire, and a spaced portion connected to the protruding portionand spaced apart from the lower surface of the first nanowire.
 12. Thesemiconductor device of claim 11, wherein the gate electrode comprisesfirst and second side surfaces opposite to each other, and wherein theprotruding portion comprises a first protruding portion which is incontact with the first side surface of the gate electrode, and a secondprotruding portion which is in contact with the second side surface ofthe gate electrode.
 13. The semiconductor device of claim 12, whereinthe gate spacer comprises a first gate spacer which is in contact withthe first side surface and a second gate spacer which is in contact withthe second side surface, wherein a thickness of the first protrudingportion is the same as that of the first gate spacer and a thickness ofthe second protruding portion is the same as that of the second gatespacer.
 14. The semiconductor device of claim 11, wherein a length ofthe inner spacer in the first direction is the same as that of the firstnanowire in the first direction.
 15. The semiconductor device of claim11, wherein the gate electrode is disposed between the spaced portionand the first nanowire.
 16. A semiconductor device, comprising: asubstrate; a first nanowire extended in a first direction and spacedapart from the substrate; a gate electrode surrounding a periphery ofthe first nanowire and extending in a second direction intersecting thefirst direction; a gate spacer disposed on a sidewall of the gateelectrode, wherein the gate spacer comprises inner and outer sidewallsopposite to each other, and the inner sidewall of the gate spacer facesthe gate electrode; a source/drain disposed on at least one side of thegate electrode and connected with the first nanowire, wherein the firstnanowire passes through the gate spacer to be connected to thesource/drain; and an inner spacer disposed between the substrate and thefirst nanowire, wherein a material included in the gate spacer has afirst dielectric constant and a material included in the inner spacerhas a second dielectric constant different from the first dielectricconstant.
 17. The semiconductor device of claim 16, wherein the seconddielectric constant is lower than the first dielectric constant.
 18. Thesemiconductor device of claim 16, further comprising a second nanowiredisposed on the first nanowire and extended in the first direction,wherein the first nanowire and the second nanowire are spaced apart fromeach other in a manner such that a height from an uppermost surface ofthe substrate to a lowermost surface of the second nanowire is greaterthan a height from the uppermost surface of the substrate to a lowermostsurface of the first nanowire.
 19. The semiconductor device of claim 18,further comprising a third nanowire disposed on the second nanowire andextended in the first direction, wherein the second nanowire and thethird nanowire are spaced apart from each other in a manner such that aheight from the uppermost surface of the substrate to a lowermostsurface of the third nanowire is greater than a height from theuppermost surface of the substrate to the lowermost surface of thesecond nanowire.
 20. The semiconductor device of claim 16, wherein alength of the inner spacer in the first direction is the same as that ofthe first nanowire in the first direction.